1. Field of the Invention
Embodiments described herein relate generally to improved semiconductor imaging devices and in particular to imaging devices having an array of pixels and to methods of operating the pixels to reduce temporal noise.
2. Background of the Invention
A conventional four transistor (4T) circuit for a pixel 150 of a CMOS imager is illustrated in FIG. 1. The 4T pixel 150 has a photosensor such as a photodiode 162, a reset transistor 184, a transfer transistor 190, a source follower transistor 186, and a row select transistor 188. It should be understood that FIG. 1 shows the circuitry for operation of a single pixel 150, and that in practical use, there will be an M×N array of pixels arranged in rows and columns with the pixels of the array being accessed using row and column select circuitry, as described in more detail below.
The photodiode 162 converts incident photons to electrons, which are selectively passed to a floating diffusion node A through transfer transistor 190 when the transistor 190 is activated by the TX1 control signal. The source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at the floating diffusion node A. When a particular row containing pixel 150 is selected by an activated row select transistor 188, the signal amplified by the source follower transistor 186 is passed on a column line 170 to column readout circuitry (not shown). The photodiode 162 accumulates a photo-generated charge in a doped region of its substrate during a charge integration period. It should be understood that the pixel 150 may include a photogate or other photon to charge converting device, in lieu of a photodiode, as the initial accumulator for photo-generated charge.
The gate of transfer transistor 190 is coupled to a transfer control signal line 191 for receiving the TX1 control signal, thereby serving to control the coupling of the photodiode 162 to node A. A voltage source Vpix is selectively coupled through reset transistor 184 and conductive line 163 to node A. The gate of reset transistor 184 is coupled to a reset control line 183 for receiving the RST control signal to control the reset operation in which the voltage source Vpix is connected to node A.
A row select signal (Row Sel) on a row select control line 160 is used to activate the row select transistor 188. Although not shown, the row select control line 160, reset control line 183, and transfer signal control line 191 are coupled to all of the pixels of the same row of the array. Voltage source Vpix is coupled to transistors 184 and 186 by conductive line 195. The column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink 176 at its lower end. Maintaining a positive voltage on the column line 170 during an image acquisition phase keeps the potential in a known state on the column line 170. Signals from the pixel 150 are therefore selectively coupled to a column readout circuit 261 (FIGS. 2-4) through the column line 170.
As is known in the art, a value can be read from pixel 150 in a two step correlated double sampling process. First, node A is reset by activating the reset transistor 184. The reset signal (e.g., Vrst) found at node A is readout to column line 170 via the source follower transistor 186 and the activated row select transistor 188. During a charge integration period, photodiode 162 produces charge from incident light. This is also known as the image acquisition period. After the integration period, transfer transistor 190 is activated and the charge from the photodiode 162 is passed through the transfer transistor 190 to node A, where the charge is amplified by source follower transistor 186 and passed to column line 170 (through the row select transistor 188) as an integrated charge signal Vsig. As a result, two different voltage signals—the reset signal Vrst and the integrated charge signal Vsig—are readout from the pixel 150 and sent on the column line 170 to column readout circuitry, where each signal is sampled and held for further processing as is known in the art. Typically, all pixels in a row are readout simultaneously onto respective column lines 170 and the column lines may be activated in sequence or in parallel for pixel reset and signal voltage readout.
FIG. 2 shows an example CMOS imager device 201 that includes an array 230 of pixels and a controller 232, which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Example arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The pixel signals from the array 230 are readout a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Signals corresponding to charges stored in the selected row of pixels and reset signals are provided on the column lines 170 to a column readout circuit 242 in the manner described above. The pixel signal read from each of the columns can be readout sequentially using a column addressing circuit 244. Pixel signals (Vrst, Vsig) corresponding to the readout reset signal and integrated charge signal are provided as respective outputs Vrst, Vsig of the column readout circuit 242 where they are subtracted in differential amplifier 275, digitized by analog-to-digital converter (ADC) 248, and sent to an image processor circuit 250 for image processing.
FIG. 3 shows more details of the rows and columns 249 of active pixels 150 in array 230. Each column 249 includes multiple rows of pixels 150. Signals from the pixels 150 in a particular column 249 can be readout to sample and hold circuitry 261 associated with the column 249 (part of circuit 242) for acquiring the pixel reset Vrst and integrated charge Vsig signals. Signals stored in the sample and hold circuits 261 can be read sequentially column-by-column to the differential amplifier 246 (FIG. 2), which subtracts the reset and integrated charge signals and sends them to the analog-to-digital converter 248 (FIG. 2). A plurality of analog-to-digital converters 248 may also be provided, each digitizing sampled and held signals from one or more columns 249.
FIG. 4 illustrates a portion of the sample and hold circuit 261 of FIG. 3 in greater detail. The sample and hold circuit 261 holds a set of signals, e.g., a reset signal Vrst and an integrated charge signal Vsig from a desired pixel. For example, a reset signal Vrst of a desired pixel connected to column line 170 is stored on capacitor 226 and the integrated charge signal Vsig is stored on capacitor 228. A front side of capacitor 226 is switchably coupled to the column line 170 through switch 222 and a backside of capacitor 226 is switchably coupled to amplifier 275 through switch 218. A front side of capacitor 228 is switchably coupled to the column line 170 through switch 220 and a backside of capacitor 228 is switchably coupled to amplifier 275 through switch 216. The front side of capacitor 226 is switchably coupled to the front side of capacitor 228 through crowbar switch 239. The backside of capacitor 226 is switchably coupled to the backside of capacitor 228 and to a reference voltage Vref source through clamp switch 299.
Each sample and hold circuit 261 is coupled to amplifier 275 having a first and a second input. The first input of amplifier 275 is coupled to a first output of amplifier 275 through a capacitor 278 and a switch 279 to provide a first feedback circuit. The second input of amplifier 275 is coupled to a second output of amplifier 275 through a capacitor 276 and a switch 277 to provide a second feedback circuit.
The conventional CMOS imager of FIGS. 1-4 has identical correlated double sampling and holding timing for all columns over an entire row. Thus, all of the pixels in a row are readout at substantially the same time. The simplified correlated double sampling and column read out timing is depicted in FIG. 5.
Thus, to begin a readout operation, a logic high clamp signal is provided to clamp switch 299 thereby coupling the backsides of capacitors 226, 228 to a reference voltage source Vref. When a reset signal is read from a pixel 150, a logic high SHR signal is provided to the gate of switch 222 thereby coupling the front side of capacitor 226 to the column line 170. When the readout of the reset signal from the pixel 150 is complete, a logic low SHR signal is provided to the gate of switch 222 thereby uncoupling the front side of capacitor 226 from the column line 170. Thus, a reset signal Vrst has been sampled and stored on capacitor 226.
After the reset Vrst signal is read from pixel 150, an integrated charge signal Vsig is read. When an integrated charge signal Vsig is read from pixel 150, a logic high SHS signal is provided to the gate of switch 220 thereby coupling the front side of capacitor 228 to the column line 170. When the readout of the integrated charge signal Vsig from the pixel 150 is complete, a logic low SHS signal is provided to the gate of switch 220 thereby uncoupling the front side of capacitor 228 from the column line 170. Thus, an integrated charge signal Vsig has been sampled and stored on capacitor 226.
When a readout operation is complete, a logic low clamp signal is provided to clamp switch 299 thereby uncoupling the backsides of capacitors 226, 228 from the reference voltage source Vref.
After a row of pixels has been readout and sampled and held, then, generally in column order, the sample and hold circuits 261 output their stored signals to the amplifier 275. When reading from a first sample and hold circuit 261, a logic high control signal Φamp is provided to the feedback circuits to close switch 279 to couple the first output of amplifier 275 through capacitor 278 to its first input and to close switch 277 to couple the second output of amplifier 275 through capacitor 276 to its second input. A logic high crowbar control signal, e.g., crowbar1 for the sample and hold circuit 261 associated with the first column, is also provided to the sample and hold circuit 261 being readout to close the associated crowbar switch 239, thereby coupling the front side of capacitor 226 to the front side of capacitor 228. A logic high control signal, e.g., cl for the sample and hold circuit 261 associated with the first column, is also provided to the sample and hold circuit 261 being readout to close switch 218 and switch 216, thereby coupling the backside of capacitor 226 to the first input of amplifier 275 and coupling the backside of capacitor 228 to the second input of amplifier 275.
After the reset and integrated charge signals have been readout to amplifier 275, a logic low control signal Φamp is provided to the feedback circuits to open switch 279 and uncouple the first output of amplifier 275 from capacitor 278 and to open switch 277 and uncouple the second output of amplifier 275 from capacitor 276. A logic low crowbar control signal is provided to the sample and hold 261 being readout to open the associated crowbar switch 239, thereby uncoupling the front side of capacitor 226 from the front side of capacitor 228 (e.g., crowbar 1 for the first column). A logic low control signal e.g., cl, is also provided to the sample and hold 261 being readout to open switch 218 and switch 216, thereby uncoupling the backside of capacitor 226 from the first input of amplifier 275 and uncoupling the backside of capacitor 228 from the second input of amplifier 275. Thus, a correlated double sampled signal is provided as output from amplifier 275 resulting from the input of the integrated charge and reset signals to the amplifier 275.
After a row of sample and hold circuits 261 have been readout, a next of row of pixels 150 in the pixel array 230 are sample and held, and then readout through the amplifier 275.
The correlated double sampled signal output by an amplifier 275 can be expressed by:
                                                                        V                CDS                            =                            ⁢                                                V                  op                                -                                  V                  on                                                                                                        =                            ⁢                                                (                                                                                                              C                          amp                                                                          C                          pr                                                                    ⁢                                              V                                                  pixel                          ⁢                          _                          ⁢                          reset                                                                                      -                                                                                            C                          amp                                                                                                      C                            nr                                                    ⁢                                                                                                                                                    ⁢                                              V                                                  noise                          ⁢                          _                          ⁢                          reset                                                                                                      )                                -                                                                                                      ⁢                              (                                                                                                    C                        amp                                                                    C                        ps                                                              ⁢                                          V                                              pixel                        ⁢                        _                        ⁢                        signal                                                                              -                                                                                    C                        amp                                                                    C                        ns                                                              ⁢                                          V                                              noise                        ⁢                        _                        ⁢                        signal                                                                                            )                                                                        (        1        )            
where Camp is the feedback capacitance of the gain stage 276, 278 of amplifier 275, Cpr is pixel_reset level sample-and-hold capacitor 226, and Cps is pixel_signal level sample-and-hold capacitor 228.
The pixel output level can be divided by terms, one for pure pixel level and the other for noise level at the sample phase:Vpixel—reset=Vpixel—reset—without—noise+Vnoise—reset  (2)andVpixel—signal=Vpixel—signal—without—noise+Vnoise—signal  (3)
where Vpixel_reset_without_noise and Vpixel_signal_without_noise are the pixel_reset and the pixel_signal levels without noise, respectively, and Vnoise_reset and Vnoise_signal levels are the noise levels during the SHR phase and SHS phase, respectively.
By utilizing equations (2) and (3), and assuming Camp=Cf and also assuming that Cs=Cps=Cpr, the correlated double sampled signal that is output can be expressed by:
                              V          CDS                =                                            C              f                                      C              s                                ⁢                      (                                          (                                                      V                                                                  pixel                        ⁢                        _                        ⁢                        reset                                            ⁢                                              _                        ⁢                        withou                        ⁢                        t                                            ⁢                                              _                        ⁢                        noise                                                                              -                                      V                                                                  pixel                        ⁢                        _                        ⁢                        signal                                            ⁢                                              _                        ⁢                        withou                        ⁢                        t                                            ⁢                                              _                        ⁢                        noise                                                                                            )                            +                              (                                                      V                                          noise                      ⁢                      _                      ⁢                      reset                                                        -                                      V                                          noise                      ⁢                      _                      ⁢                      signal                                                                      )                                      )                                              (        4        )            
If the noise levels of the readout from the sample and hold circuit 261 at both falling edges of SHR and SHS are same, then the correlated double sampled signal output from amplifier 275 is provided without significant row noise. As seen for example, in FIG. 6, the noise in the circuit is at the same level throughout SHR and SHS; thus, the correlated double sampled signal output from amplifier 275 of the column output is provided without significant row noise. Thus, the signal on the column output is substantially 0 v after the correlated double sampled signal is output. Thus, there is no residual noise on the column circuit that affects subsequent columns being readout.
However, if the noise levels of the readout from the sample and hold circuit 261 at both falling edges of SHR and SHS are not same, then the correlated double sampled signal output from amplifier 275 has some significant row noise, as represented by a spike on the noise line in FIG. 7. As seen for example, in FIG. 7, the noise in circuit 261 is not at the same level throughout the SHR and SHS active periods, thus, the correlated double sampled signal output from amplifier 275 is provided with row noise. Thus, the signal on the column output is greater than 0 v and likely equal to the noise level after the correlated double sampled signal is output. This is depicted on the bottom line of FIG. 7, where the residual noise remains in the column circuit after the correlated double sampled signal is output. This residual noise on the column circuit affects subsequent rows being readout.
Thus, it is desirable to have a readout of signals from a pixel array with reduced row-wise temporal noise.